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october 2007 rev 14 1/69 1 M58BW016DB m58bw016dt m58bw016ft m58bw016fb 16 mbit (512 kb x 32, boot block, burst) 3 v supply flash memories features supply voltage ?v dd = 2.7 v to 3.6 v for program, erase and read ?v ddq = v ddqin = 2.4 v to 3.6 v for i/o buffers ?v pp = 12 v for fast program (optional) high performance ? access times: 70, 80 ns ? 56 mhz effective zero wait-state burst read ? synchronous burst read ? asynchronous page read hardware block protection ?wp pin for write protect of the 4 outermost parameter blocks and all main blocks ?rp pin for write protect of all blocks optimized for fdi drivers ? fast program / erase suspend latency time < 6 s ? common flash interface memory blocks ? 8 parameters blocks (top or bottom) ? 31 main blocks low power consumption ? 5 a typical deep power-down ? 60 a typical standby for m58bw016dt/b 150 a typical standby for m58bw016ft/b ? automatic standby after asynchronous read electronic signature ? manufacturer code: 20h ? top device code: 8836h ? bottom device code: 8835h ecopack ? packages available pqfp80 (t) bga lbga80 10 12 mm www.st.com
contents m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 2/69 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 address inputs (a0-a18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 data inputs/outputs (dq0-dq31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 output disable (gd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 reset/power-down (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.9 burst clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 burst address advance (b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.11 valid data ready (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.12 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.13 supply voltage (v dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.14 output supply voltage (v ddq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.15 input supply voltage (v ddqin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.16 program/erase supply voltage (v pp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.17 ground (v ss and v ssq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.18 don?t use (du) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.19 not connected (nc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.2 asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . 18 3.1.3 asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.4 asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.5 asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . 19 3.1.6 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb contents 3/69 3.1.7 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.8 automatic low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.9 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.10 electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 read select bit (m15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.2 x-latency bits (m14-m11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.3 y-latency bit (m9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.4 valid data ready bit (m8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.5 burst type bit (m7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.6 valid clock edge bit (m6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.7 wrap burst bit (m3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3.8 burst length bit (m2-m0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 read query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10 set burst configuration register command . . . . . . . . . . . . . . . . . . . . . . . 32 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.1 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.4 program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.5 v pp status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
contents m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 4/69 5.6 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.7 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 appendix a common flash interface (c fi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 appendix b flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb list of tables 5/69 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. m58bw016dt and m58bw016ft top boot block addresses . . . . . . . . . . . . . . . . . . . . . . 12 table 3. M58BW016DB and m58bw016fb bottom boot block addresses . . . . . . . . . . . . . . . . . . . 13 table 4. asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. asynchronous read electronic signature operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. burst configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. program, erase time s and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . 33 table 11. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 14. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16. asynchronous bus read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17. asynchronous latch controlled bus read ac characteristics . . . . . . . . . . . . . . . . . . . . . . 42 table 18. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19. asynchronous write and latch controlled write ac characteristics . . . . . . . . . . . . . . . . . 46 table 20. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 22. pqfp80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . . 52 table 23. lbga80 10 12 mm - 8 10 active ball array, 1 mm pitch, package mechanical data . . 53 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 25. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 26. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 27. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 28. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 29. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
list of figures m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 6/69 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pqfp connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. lbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. example burst configuration x-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 5. example burst configuration x-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 6. ac measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 8. asynchronous bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 9. asynchronous latch controlled bus read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 10. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 11. asynchronous write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 12. asynchronous latch controlled write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 13. synchronous burst read (data valid from ?n? clock rising edge). . . . . . . . . . . . . . . . . . . . . 47 figure 14. synchronous burst read (data valid from ?n? clock rising edge). . . . . . . . . . . . . . . . . . . . . 48 figure 15. synchronous burst read - continuous - valid data ready output . . . . . . . . . . . . . . . . . . . . 49 figure 16. synchronous burst read - burst address advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 17. reset, power-down and power-up ac waveforms - control pins low. . . . . . . . . . . . . . . . . 50 figure 18. reset, power-down and power-up ac waveforms - control pins toggling . . . . . . . . . . . . . 50 figure 19. pqfp80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 20. lbga80 10 12 mm - 8 10 active ball array, 1 mm pitch, package outline . . . . . . . . . . 53 figure 21. program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 figure 22. program suspend & resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 23. block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 24. erase suspend & resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 25. power-up sequence followed by synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 26. command interface and program/erase controller flowchart (a) . . . . . . . . . . . . . . . . . . . . 63 figure 27. command interface and program/erase controller flowchart (b) . . . . . . . . . . . . . . . . . . . . 64 figure 28. command interface and program/erase controller flowchart (c) . . . . . . . . . . . . . . . . . . . . 65 figure 29. command interface and program/erase controller flowchart (d) . . . . . . . . . . . . . . . . . . . . 66
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb description 7/69 1 description the m58bw016dt, M58BW016DB, m58bw016ft and m58bw016fb are 16 mbit non- volatile flash memories that can be erased electrically at the block level and programmed in-system on a double-word basis using a 2.7 v to 3.6 v v dd supply for the circuit and a v ddq supply down to 2.4 v for the input and output buffers. optionally a 12 v v pp supply can be used to provide fast program and erase for a limited time and number of program/erase cycles. the devices support asynchronous (latch controlled and page read) and synchronous bus operations. the synchronous burst read in terface allows a high data transfer rate controlled by the burst clock, k, signal. it is capable of bursting fixed or unlimited lengths of data. the burst type, latency and length can be configured and can be easily adapted to a large variety of system clock frequencies and microprocessors. all writes are asynchronous. on power-up the memory defaults to read mode with an asynchronous bus. the devices have a boot block architecture with an array of 8 parameter blocks of 64 kb each and 31 main blocks of 512 kb each. in the m58bw016dt and m58bw016ft the parameter blocks are located at the top of the address space whereas in the M58BW016DB and m58bw016fb, they are located at the bottom. program and erase commands are written to the command interface of the memory. an on- chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. erase can be suspended in order to perform either read or program in any other block and then resumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. all blocks are protected during power-up. the m58bw016dt, M58BW016DB, m58bw016ft and m58bw016fb feature two different levels of block protection to avoid unwanted program/erase operations: the wp pin offers an hardware protection on two of the parameter blocks and all of the main blocks all program or erase operations are blocked when reset, rp, is held low. a reset/power-down mode is entered when the rp input is low. in this mode the power consumption is lower than in the normal standby mode, the device is write protected and both the status and the burst configuration registers are cleared. a recovery time is required when the rp input goes high. the memory is offered in a pqfp80 (14 x 20 mm) and lbga80 (10 12 mm) package. in order to meet environmental requirements, st offers the devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . the memories are supplied with all the bits erased (set to ?1?).
description m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 8/69 in the present document, m58bw016dt, M58BW016DB, m58bw016ft and m58bw016fb will be referred to as m58bw016 unless otherwise specified. figure 1. logic diagram ai11201b a0-a18 l dq0-dq31 v dd m58bw016dt M58BW016DB m58bw016ft m58bw016fb e v ss rp g gd v ddq w wp r k v pp b v ssq v ddqin
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb description 9/69 table 1. signal names signal description direction a0-a18 address inputs inputs dq0-dq7 data input/output, command input i/o dq8-dq15 data input/output, burst configuration register i/o dq16-dq31 data input/output i/o b burst address advance input e chip enable input g output enable input k burst clock input l latch enable input r valid data ready (open drain output) output rp reset/power-down input w write enable input gd output disable input wp write protect input v dd supply voltage v ddq power supply for output buffers v ddqin power supply for input buffers only v pp optional supply voltage for fast program and fast erase operations v ss ground v ssq input/output ground nc not connected internally du don?t use as internally connected
description m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 10/69 figure 2. pqfp connections (top view through package) ai11202b 12 1 73 53 v ddq dq24 dq25 dq18 dq17 dq16 dq19 dq20 dq21 dq22 dq23 v ddq dq29 dq26 dq30 du dq31 dq28 dq27 a2 a5 a3 a4 a0 a1 a11 v ss a12 a13 a14 a10 gd wp w du g v ss e k l nc b rp v ddq dq7 dq6 dq13 dq14 dq15 dq12 dq11 dq10 dq9 v ssq dq8 dq2 dq5 dq0 nc a18 a16 a17 dq3 dq4 v ssq v ssq a8 a6 a7 v pp v dd a9 a15 dq1 v ddq v ssq r v dd nc v ddqin 24 25 32 40 41 64 65 80 m58bw016dt M58BW016DB m58bw016ft m58bw016fb
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb description 11/69 figure 3. lbga connections (top view through package) 1.1 block protection the m58bw016 feature two different levels of block protection. write protect pin, wp , - when wp is low, v il , all the lockable parameter blocks (two upper (top) or lower (bottom)) and all the main blocks are protected. when wp is high (v ih ) all the lockable parameter blocks and all the main blocks are unprotected reset/power-down pin, rp , - if the device is held in reset mode (rp at v il ), no program or erase operations can be performed on any block. after a device reset the first two kinds of block protection (wp , rp ) can be combined to give a flexible block protection. ai04151c b dq24 dq7 v ssq f v ddq dq26 dq4 v ddq e dq29 v ss dq0 dq3 d a0 nc a7 a11 a18 a17 c a1 a4 a5 a8 rp e a13 a16 b a2 a3 a6 v dd v pp v dd a14 a 8 7 6 5 4 3 2 1 dq20 dq18 dq19 dq17 dq11 dq12 dq13 v ddq dq23 dq8 v ddq h g nc gd w v ddqin dq16 r g l dq14 dq15 j i a15 v ss a12 a9 a10 nc nc nc dq31 dq30 dq2 dq28 dq6 dq25 v ssq dq10 dq9 dq21 wp k nc dq1 dq27 dq5 nc dq22
description m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 12/69 table 2. m58bw016dt and m58bw016ft top boot block addresses # size (kbit) address range 38 64 7f800h-7ffffh 37 64 7f000h-7f7ffh 36 64 7e800h-7efffh 35 64 7e000h-7e7ffh 34 64 7d800h-7dfffh 33 64 7d000h-7d7ffh 32 64 7c800h-7cfffh 31 64 7c000h-7c7ffh 30 512 78000h-7bfffh 29 512 74000h-77fffh 28 512 70000h-73fffh 27 512 6c000h-6ffffh 26 512 68000h-6bfffh 25 512 64000h-67fffh 24 512 60000h-63fffh 23 512 5c000h-5ffffh 22 512 58000h-5bfffh 21 512 54000h-57fffh 20 512 50000h-53fffh 19 512 4c000h-4ffffh 18 512 48000h-4bfffh 17 512 44000h-47fffh 16 512 40000h-43fffh 15 512 3c000h-3ffffh 14 512 38000h-3bfffh 13 512 34000h-37fffh 12 512 30000h-33fffh 11 512 2c000h-2ffffh 10 512 28000h-2bfffh 9 512 24000h-27fffh 8 512 20000h-23fffh 7 512 1c000h-1ffffh 6 512 18000h-1bfffh 5 512 14000h-17fffh 4 512 10000h-13fffh 3 512 0c000h-0ffffh 2 512 08000h-0bfffh 1 512 04000h-07fffh 0 512 00000h-03fffh
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb description 13/69 table 3. M58BW016DB and m58bw016fb bottom boot block addresses # size (kbit) address range 38 512 7c000h-7ffffh 37 512 78000h-7bfffh 36 512 74000h-77fffh 35 512 70000h-73fffh 34 512 6c000h-6ffffh 33 512 68000h-6bfffh 32 512 64000h-67fffh 31 512 60000h-63fffh 30 512 5c000h-5ffffh 29 512 58000h-5bfffh 28 512 54000h-57fffh 27 512 50000h-53fffh 26 512 4c000h-4ffffh 25 512 48000h-4bfffh 24 512 44000h-47fffh 23 512 40000h-43fffh 22 512 3c000h-3ffffh 21 512 38000h-3bfffh 20 512 34000h-37fffh 19 512 30000h-33fffh 18 512 2c000h-2ffffh 17 512 28000h-2bfffh 16 512 24000h-27fffh 15 512 20000h-23fffh 14 512 1c000h-1ffffh 13 512 18000h-1bfffh 12 512 14000h-17fffh 11 512 10000h-13fffh 10 512 0c000h-0ffffh 9 512 08000h-0bfffh 8 512 04000h-07fffh 7 64 03800h-03fffh 6 64 03000h-037ffh 5 64 02800h-02fffh 4 64 02000h-027ffh 3 64 01800h-01fffh 2 64 01000h-017ffh 1 64 00800h-00fffh 0 64 00000h-007ffh
signal descriptions m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 14/69 2 signal descriptions see figure 1: logic diagram , and table 1: signal names for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a18) the address inputs are used to select the cells to access in the memory array during bus operations either to read or to program data. during bus write operations they control the commands sent to the command interface of the program/erase controller. chip enable must be low when selecting the addresses. the address inputs are latched on the rising edge of latch enable l or burst clock k, whichever occurs first, in a read operation.the address inputs are latched on the rising edge of chip enable, write enable or latch enable , whichever occurs first in a write operation. the address latch is transparent when latch enable is low, v il . the address is internally latched in an erase or program operation. 2.2 data inputs/outputs (dq0-dq31) the data inputs/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. during bus write operations they represent the commands sent to the command interface of the program/erase controller. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , and output disable is at v ih, the data bus outputs data from the memory array, the electronic signature, the cfi information or the contents of the status register. the data bus is high impedance when the device is deselected with chip enable at v ih , output enable at v ih , output disable at v il or reset/power-down at v il . the status register content is output on dq0-dq7 and dq8- dq31 are at v il . 2.3 chip enable (e ) the chip enable, e , input activates the memory control logic, input buffers, decoders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level. 2.4 output enable (g ) the output enable, g , gates the outputs through the data output buffers during a read operation, when output disable gd is at v ih . when output enable g is at v ih , the outputs are high impedance independently of output disable.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb signal descriptions 15/69 2.5 output disable (gd ) the output disable, gd , deactivates the data output buffers. when output disable, gd , is at v ih , the outputs are driven by the output enable. when output disable, gd , is at v il , the outputs are high impedance independently of output enable. the output disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. 2.6 write enable (w ) the write enable, w , input controls writing to the command interface, address inputs and data latches. both addresses and data can be latched on the rising edge of write enable (also see latch enable, l ). 2.7 reset/power-down (rp ) the reset/power-down, rp , is used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset/power-down low, v il , for at least t plph . writing is inhibited to protect data, the command interface and the program/erase controller are reset. the status register information is cleared and power consumption is reduced to deep power-down level. the device acts as deselected, that is the data outputs are high impedance. after reset/power-down goes high, v ih , the memory will be ready for bus read operations after a delay of t phel or bus write operations after t phwl . if reset/power-down goes low, v il , during a block erase, or a program the operation is aborted, in a time of t plrh maximum, and data is altered and may be corrupted. during power-up power should be applied simultaneously to v dd and v ddq(in) with rp held at v il . when the supplies are stable rp is taken to v ih . output enable, g , chip enable, e , and write enable, w , should be held at v ih during power-up. in an application, it is recommended to associate reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset operation occurs while the memory is performing an erase or program operation, the memory may output the status register information instead of being initialized to the default asynchronous random read. see table 21: reset, power-down and power-up ac characteristics and figure 17: reset, power-down and power-up ac waveforms - control pins low , for more details. 2.8 latch enable (l ) the bus interface can be configured to latch the address inputs on the rising edge of latch enable, l , for asynchronous latch enable controlled read or write or synchronous burst read operations. in synchronous burst read operations the address is latched on the active edge of the clock when latch enable is low, v il . once latched, the addresses may change without affecting the address used by the memory. when latch enable is low, v il , the latch is transparent. latch enable, l , can remain at v il for asynchronous random read and write operations.
signal descriptions m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 16/69 2.9 burst clock (k) the burst clock, k, is used to synchronize the memory with the external bus during synchronous burst read operations. bus signals are latched on the active edge of the clock. the clock can be configur ed to have an active rising or falling edge. in synchronous burst read mode the address is latched on the first active clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. 2.10 burst address advance (b ) the burst address advance, b , controls the advancing of the address by the internal address counter during synchronous burst read operations. burst address advance, b , is only sampled on the active clock edge of the clock when the x-latency time has expired. if burst address advance is low, v il , the internal address counter advances. if burst address advance is high, v ih , the internal address counter does not change; the same data remains on the data inputs/outputs and burst address advance is not sampled until the y-latency expires. the burst address advance, b , may be tied to v il . 2.11 valid data ready (r) the valid data ready output, r, is an open drain output that can be used, during synchronous burst read operations, to identify if the memory is ready to output data or not. the valid data ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. valid data ready, at v ih , indicates that new data is or will be available. when valid data ready is low, v il , the previous data outputs remain active. in all asynchronous operations, valid data ready is high-impedance. it may be tied to other components with the same valid data ready signal to create a unique system ready signal. the valid data ready output has an internal pull-up resistor of around 1 m ? powered from v ddq , designers should use an external pull-up resistor of the correct value to meet the external timing requirements for valid data ready going to v ih . 2.12 write protect (wp ) the write protect, wp , provides protection against program or erase operations. when write protect, wp , is at v il the first two (in the bottom configuration) or last two (in the top configuration) parameter blocks and all main blocks are locked. when write protect wp is at v ih all the blocks can be programmed or erased, if no other protection is used. 2.13 supply voltage (v dd ) the supply voltage, v dd , is the core power supply. all internal circuits draw their current from the v dd pin, including the program/erase controller.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb signal descriptions 17/69 2.14 output supply voltage (v ddq ) the output supply voltage, v ddq , is the output buffer power supply for all operations (read, program and erase) used for dq0-dq31 when used as outputs. 2.15 input supply voltage (v ddqin ) the input supply voltage, v ddin , is the power supply for all input signal. input signals are: k, b , l , w , gd , g , e , a0-a18 and dq0-dq31, when used as inputs. 2.16 program/erase supply voltage (v pp ) the program/erase supply voltage, v pp , is used for program and erase operations. the memory normally executes program and erase operations at v pp1 voltage levels. in a manufacturing environment, programming may be speeded up by applying a higher voltage level, v pph , to the v pp pin. the voltage level v pph may be applied for a total of 80 hours over a maximum of 1000 cycles. stressing the device beyond these limits could damage the device. 2.17 ground (v ss and v ssq ) the ground v ss is the reference for the internal supply voltage v dd . the ground v ssq is the reference for the output and input supplies v ddq, and v ddqin . it is essential to connect v ss and v ssq together. note: a 0.1 f capacitor should be connected between the supply voltages, v dd , v ddq and v ddin and the grounds, v ss and v ssq to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during all operations of the parts, see table 15: dc characteristics , for maximum current supply requirements. 2.18 don?t use (du) this pin should not be used as it is internally connected. its voltage level can be between v ss and v ddq or leave it unconnected. 2.19 not connected (nc) this pin is not physically connected to the device.
bus operations m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 18/69 3 bus operations each bus operation that controls the memory is described in this section, see ta b l e 4 , ta bl e 5 and ta bl e 6 bus operations, for a summary. the bus operation is selected through the burst configuration register; the bits in this register are described at the end of this section. on power-up or after a hardware reset the memory defaults to asynchronous bus read and asynchronous bus write, no other bus operation can be performed until the burst control register has been configured. the electronic signature, cfi or status register will be re ad in asynchronous mode regardless of the burst control register settings. typically glitches of less than 5 ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 asynchronous bus operations for asynchronous bus operations refer to ta bl e 4 together with the following text. 3.1.1 asynchronous bus read asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, status register, cfi and burst configuration register) in the command interface. a valid bus operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable and output disable high, v ih . the data inputs/outputs will output the value, see figure 8: asynchronous bus read ac waveforms , and table 16: asynchronous bus read ac characteristics , for details of when the output becomes valid. asynchronous read is the default read mode which the device enters on power-up or on return from reset/power-down. 3.1.2 asynchronous latch controlled bus read asynchronous latch controlled bus read operations read from the memory cells or specific registers in the command interface. the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip enable and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the rising edge of latch enable. once latched, the address inputs can change. set output enable low, v il , to read the data on the data inputs/outputs; see figure 9: asynchronous latch controlled bus read ac waveforms , and table 17: asynchronous latch controlled bus read ac characteristics , for details on when the output becomes valid. note that, since the latch enable input is transparent when set low, v il , asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding latch enable low, v il throughout the bus operation.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb bus operations 19/69 3.1.3 asynchronous page read asynchronous page read operations are used to read from several addresses within the same memory page. each memory page is 4 double-words and is addressed by the address inputs a0 and a1. data is read internally and stored in the page buffer. valid bus operations are the same as asynchronous bus read operations but with different timings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings apply again. page read does not support latched controlled read. see figure 10: asynchronous page read ac waveforms , and table 18: asynchronous page read ac characteristics , for details on when the outputs become valid. 3.1.4 asynchronous bus write asynchronous bus write operations write to the command interface to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is don?t care during bus write operations. a valid asynchronous bus write operation begins by setting the desired address on the address inputs, and setting chip enable, write enable and latch enable low, v il , and output enable high, v ih , or output disable low, v il . the address inputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 11: asynchronous write ac waveforms , and table 19: asynchronous write and latch controlled write ac characteristics , for details of the timing requirements. 3.1.5 asynchronous latch controlled bus write asynchronous latch controlled bus write operations write to the command interface to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is don?t care during bus write operations. a valid asynchronous latch controlled bus write operation begins by setting the desired address on the address inputs and pulsing latch enable low, v il . the address inputs are latched by the command interface on the rising edge of latch enable, write enable or chip enable, whichever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 12: asynchronous latch controlled write ac waveforms , and ta b l e 1 9 : asynchronous write and latch controlled write ac characteristics , for details of the timing requirements. 3.1.6 output disable the data outputs are high impedance when the output enable, g , is at v ih or output disable, gd , is at v il .
bus operations m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 20/69 3.1.7 standby mode when chip enable is high, v ih , and the program/erase controller is idle, the memory enters standby mode, the power consumption is reduced to the standby level and the data inputs/outputs pins are placed in the high impedance state regardless of output enable, write enable or output disable inputs. 3.1.8 automatic low power mode if there is no change in the state of the bus for a short period of time during asynchronous bus read operations the memory enters auto low power mode where the internal supply current is reduced to the auto-standby suppl y current. the data inputs/outputs will still output data if a bus read operation is in progress. automatic low power is only ava ilable in asynchronous read modes. 3.1.9 power-down mode the memory is in power-down when reset/power-down, rp , is at v il . the power consumption is reduced to the power-down level and the outputs are high impedance, independent of the chip enable, e , output enable, g , output disable, gd , or write enable, w, inputs. 3.1.10 electronic signature two codes identifying the manufacturer and the device can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. the electronic signature is output by giving the read electronic signature command. the manufacturer code is output when all the address inputs are at v il . the device code is output when a1 is at v ih and all the other address pins are at v il (see table 5: asynchronous read electronic signature operation ). issue a read memory array command to return to read mode. table 4. asynchronous bus operations (1) 1. x = don?t care. bus operation step e g gd w rp l a0-a18 dq0-dq31 asynchronous bus read v il v il v ih v ih v ih v il address data output asynchronous latch controlled bus read address latch v il v ih v ih v il v ih v il address high-z read v il v il v ih v ih v ih v ih x data output asynchronous page read v il v il v ih v ih v ih x address data output asynchronous bus write v il v ih xv il v ih v il address data input asynchronous latch controlled bus write address latch v il v il v ih v ih v ih v il address high-z write v il v ih xv il v ih v ih x data input output disable, g v il v ih v ih v ih v ih x x high-z output disable, gd v il v il v il v ih v ih x x high-z standby v ih xxxv ih x x high-z reset/power-down x x x x v il x x high-z
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb bus operations 21/69 3.2 synchronous bus operations for synchronous bus operations refer to ta bl e 6 together with the following text. 3.2.1 synchronous burst read synchronous burst read operati ons are used to read from the memory at specific times synchronized to an external reference clock. in the m58bw016ft and m58bw016fb only, once the memory is configured in burst mode, it is mandatory to have an active clock signal since the switching of the output buffer data bus is synchronized to the active edge of the clock. in the absence of clock, no data is output. caution: the m58bw016dt and M58BW016DB are not concerned by the paragraph above. the burst type, length and latency can be configured. the different configurations for synchronous burst read oper ations are described in section 3.3: burst configuration register . refer to figure 4 and figure 5 for examples of synchronous burst operations. in continuous burst read, one burst read operation can access the entire memory sequentially by keeping the burst address advance b at v il for the appropriate number of clock cycles. at the end of the memory address space the burst read restarts from the beginning at address 000000h. a valid synchronous burst read operation begins when the burst clock is active and chip enable and latch enable are low, v il . the burst start address is latched and loaded into the internal burst address co unter on the valid burst clock k edge (rising or falling depending on the value of m6) or on the rising edge of latch enable, whichever occurs first. after an initial memory latency time, the memory outputs data each clock cycle (or two clock cycles depending on the value of m9). the burst address advance b input controls the memory burst output. the second burst output is on the next clock valid edge after the burst address advance b has been pulled low. valid data ready, r, monitors if the memory burst boundary is exceeded and the burst controller of the microprocessor needs to insert wait states. when valid data ready is low on the active clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if burst address advance, b , is low. table 5. asynchronous read electronic signature operation code device e g gd w a18-a0 dq31-dq0 manufacturer all v il v il v ih v ih 00000h 00000020h device m58bw016dt m58bw016ft v il v il v ih v ih 00001h 00008836h M58BW016DB m58bw016fb v il v il v ih v ih 00001h 00008835h burst configuration register v il v il v ih v ih 00005h bcr (1) 1. bcr = burst configuration register.
bus operations m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 22/69 valid data ready may be configured (by bit m8 of burst configuration register) to be valid immediately at the valid clock edge or one data cycle before the valid clock edge. synchronous burst read will be suspe nded if burst address advance, b , goes high, v ih . if output enable is at v il and output disable is at v ih , the last data is still valid. if output enable, g , is at v ih or output disable, gd , is at v il , but the burst address advance, b , is at v il the internal burst address counter is incremented at each burst clock k valid edge. the synchronous burst read timing diagrams and ac characteristics are described in the ac and dc parameters section. see figure 13 , figure 14 , figure 15 and figure 16 , and ta bl e 2 0 . 3.2.2 synchronous burst read suspend during a synchronous burst read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. a valid synchronous burst read operation is suspended when both output enable and burst address advance are high, v ih . the burst address advance going high, v ih , stops the burst counter and the output enable going high, v ih , inhibits the data outputs. the synchronous burst read operation can be resumed by setting output enable low. table 6. synchronous burst read bus operations (1)(2) 1. x = don't care, v il or v ih . 2. m15 = 0, bit m15 is in the burst configuration register. bus operation step e g gd rp k (3) 3. t = transition, see m6 in the burst configuration register for details on the active edge of k. l b a0-a18 dq0-dq31 synchronous burst read address latch v il v ih xv ih tv il x address input read v il v il v ih v ih tv ih v il data output read suspend v il v ih xv ih xv ih v ih high-z read resume v il v il v ih v ih tv ih v il data output burst address advance v il v ih xv ih tv ih v il high-z read abort, e v ih xxv ih xxx high-z read abort, rp xxxv il xxx high-z
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb bus operations 23/69 3.3 burst configuration register the burst configuration register is used to configure the type of bus access that the memory will perform. the burst configuration register is set thro ugh the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into reset/power- down mode. the burst configuration register bits are described in ta b l e 7 . they specify the selection of the burst length, burst type, burst x and y latencies and the read operation. refer to figure 4 and figure 5 for examples of synchronous burst configurations. 3.3.1 read select bit (m15) the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to ?1?, bus read operations are asynchronous; when the read select but is set to ?0?, bus read operations are synchronous. on reset or power-up the read select bit is set to?1? for asynchronous accesses. 3.3.2 x-latency bits (m14-m11) the x-latency bits are used during synchronous bus read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in table 7: burst configuration register . the x-latency bits should also be selected in conjunction with table 8: burst type definition to ensure valid settings. 3.3.3 y-latency bit (m9) the y-latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. the y-latency value depends on both the x- latency value and the setting in m9. when the y-latency is ?1? the data changes each clock cycle; when the y-latency is ?2? the data changes every second clock cycle. see table 7: burst configuration register , and table 8: burst type definition for valid combinations of the y-latency, the x-latency and the clock frequency. 3.3.4 valid data ready bit (m8) the valid data ready bit controls the timing of the valid data ready output pin, r. when the valid data ready bit is ?0? the valid data ready output pin is driven low for the active clock edge when invalid data is output on the bus. when the valid data ready bit is ?1? the valid data ready ou tput pin is driven low one clock cycle prior to invalid data being output on the bus. 3.3.5 burst type bit (m7) the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is ?0? the memory outputs from interleaved addresses; when the burst type bit is ?1? the memory outputs from sequential addresses. see ta bl e 8 : burst type definition , for the sequence of addresses output from a given starting address in each mode.
bus operations m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 24/69 3.3.6 valid clock edge bit (m6) the valid clock edge bit, m6, is used to configure the active edge of the clock, k, during synchronous burst read operatio ns. when the valid clock edge bit is ?0? the falling edge of the clock is the active edge; when the valid clock edge bit is ?1? the rising edge of the clock is active. 3.3.7 wrap burst bit (m3) the burst reads can be confined inside the 4 or 8 double-word boundary (wrap) or overcome the boundary (no wrap). the wrap burst bit is used to select between wrap and no wrap. when the wrap burst bit is set to ?0? the burst read wraps; when it is set to ?1? the burst read does not wrap. 3.3.8 burst length bit (m2-m0) the burst length bits set the maximum number of double-words that can be output during a synchronous burst read operation before the address wraps. burst lengths of 4 or 8 are available for both the sequential and interleaved burst types, and a continuous burst is available for the sequential type. table 7: burst configuration register gives the valid combinations of the burst length bits that the memory accepts; table 8: burst type definition , gives the sequence of addresses output from a given starting address for each length. if either a continuous or a no wrap burst read has been initiated the device will output data synchronously. depending on the starting address, the device activates the valid data ready output to indicate that a delay is necessary before the data is output. if the starting address is aligned to an 8 double-word boundary, the co ntinuous burst mode will run without activating the valid data ready output. if the starting address is not aligned to an 8 double-word boundary, valid data ready is activated to indicate that the device needs an internal delay to read the successive words in the array. m10, m5 and m4 are reserved for future use.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb bus operations 25/69 table 7. burst configuration register bit description value description m15 read select 0 synchronous burst read 1 asynchronous read (default at power-on) m14 0 reserved (default value) m13-m11 x-latency (1) 1. x latencies can be calculated as: (t avqv ? t llkh + t qvkh ) + t system margin < (x -1) t k . (x is an integer number from 4 to 8, t k is the clock period and t system margin is the time margin required for the calculation). 000 reserved (default value) 001 reserved 010 reserved 011 5, 5-1-1-1, 5-2-2-2 100 6, 6-1-1-1, 6-2-2-2 101 7, 7-1-1-1, 7-2-2-2 110 8, 8-1-1-1, 8-2-2-2 111 reserved m10 0 reserved (default value) m9 y-latency (2) 2. y latencies can be calculated as: t khqv + t system margin + t qvkh < y t k. 0 one burst clock cycle (default value) 1 two burst clock cycles m8 valid data ready 0 r valid low during valid burst clock edge (default value) 1 r valid low 1 data cycle before valid burst clock edge m7 burst type 0 interleaved (default value) 1 sequential m6 valid clock edge 0 falling burst clock edge (default value) 1 rising burst clock edge m5-m4 00 reserved (default value) 01 reserved 10 reserved 11 reserved m3 wrapping 0 wrap (default value) 1 no wrap m2-m0 burst length 000 reserved (default value) 001 4 double-words 010 8 double-words 011 reserved 100 reserved 101 reserved 110 reserved 111 continuous
bus operations m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 26/69 table 8. burst type definition m 3 starting address x4 sequential x4 interleaved x8 sequential x8 interleaved continuous 0 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2 -3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 0 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3 -2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11.. 0 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0 -1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12.. 0 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1 -0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13.. 0 4 ? ? 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14.. 0 5 ? ? 5-6-7-0-1-2-3-4 5-4-7-6-1-0 -3-2 5-6-7-8-9-10-11-12-13-14.. 0 6 ? ? 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0 -1 6-7-8-9-10-11-12-13-14-15.. 0 7 ? ? 7-0-1-2-3-4-5-6 7-6-5-4-3-2 -1-0 7-8-9-10-11-12-13-14-15-16.. 0 8 ? ? ? ? 8-9-10-11-12-13-14-15-16-17.. 1 0 0-1-2-3 ? 0-1-2-3-4-5-6-7 ? 0-1-2-3-4-5-6-7-8-9-10.. 1 1 1-2-3-4 ? 1-2-3-4-5-6-7-8 ? 1-2-3-4-5-6-7-8-9-10-11.. 1 2 2-3-4-5 ? 2-3-4-5-6-7-8-9 ? 2-3-4-5-6-7-8-9-10-11-12.. 1 3 3-4-5-6 ? 3-4-5-6-7-8-9-10 ? 3 -4-5-6-7-8-9-10-11-12-13.. 1 4 4-5-6-7 ? 4-5-6-7-8-9-10-11 ? 4 -5-6-7-8-9-10-11-12-13-14.. 1 5 5-6-7-8 ? 5-6-7-8-9-10-11-12 ? 5-6-7-8-9-10-11-12-13-14.. 1 6 6-7-8-9 ? 6-7-8-9-10-11-12-13 ? 6-7-8-9-10-11-12-13-14-15.. 1 7 7-8-9-10 ? 7-8-9-10-11-12-13-14 ? 7-8-9-10-11-12-13-14-15-16.. 1 8 8-9-10-11 ? 8-9-10-11-12-13-14-1 5 ? 8-9-10-11-12-13-14-15-16-17..
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb bus operations 27/69 figure 4. example burst configuration x-1-1-1 figure 5. example burst configuration x-2-2-2 ai03841 k dq l add valid dq dq dq dq 4-1-1-1 5-1-1-1 6-1-1-1 7-1-1-1 8-1-1-1 0123456789 valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid ai04406b k l add dq valid dq dq dq 5-2-2-2 6-2-2-2 7-2-2-2 8-2-2-2 0123456789 valid valid valid valid valid valid valid valid nv nv nv nv nv nv nv nv nv nv nv=not valid
command interface m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 28/69 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. the commands are summarized in table 9: commands . refer to ta b l e 9 in conjunction with the text descriptions below. 4.1 read memory array command the read memory array command returns th e memory to read mode. one bus write cycle is required to issue the read memory array command and return the memory to read mode. subsequent re ad operations will output the addr essed memory array data. once the command is issued the memory remains in read mode until another command is issued. from read mode bus read commands will access the memory array. 4.2 read electronic signature command the read electronic signature command is used to read the manufacturer code, the device code or the burst configuration register. one bus write cycle is required to issue the read electronic signature command. once the command is issued subsequent bus read operations, depending on the address specified, read the manufacturer code, the device code or the burst configuration register until another command is issued; see ta bl e 5 : asynchronous read electronic signature operation . 4.3 read query command the read query command is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations, depending on the address specified, read from the common flash interface memory area. see appendix a: common flash interface (cfi) , ta bl e 2 5 , ta b l e 2 6 , ta bl e 2 7 , ta b l e 2 8 and ta bl e 2 9 for details on the information contained in the common flash interface (cfi) memory area.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb command interface 29/69 4.4 read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status r egister command. once the command is issued subsequent bus read operations read the status register until another command is issued. the status register information is present on the output data bus (dq1-dq7) when chip enable e and output enable g are at v il and output disable is at v ih . an interactive update of the status register bits is possible by toggling output enable or output disable. it is also possible during a program or erase operation, by deactivating the device with chip enable at v ih and then reactivating it with chip enable and output enable at v il and output disable at v ih . the content of the status register may also be read at the completion of a program, erase or suspend operation. during a block erase or program command, dq7 indicates the program/erase controller status. it is valid until the operation is completed or suspended. see the section on the status register and ta b l e 1 1 for details on the definitions of the status register bits. 4.5 clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to ?0?. one bus write is required to issue the clear status register command. once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to output the same data. the bits in the status register are sticky and do not automatically return to ?0? when a new program or erase command is issued. if any error occurs then it is essential to clear any error bits in the status register by issuing the clear status register command before attempting a new program, erase or resume command.
command interface m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 30/69 4.6 block erase command the block erase command can be used to erase a block. it sets all of the bits in the block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block wi ll not be changed and the status register will ou tput the error. two bus write operations are required to issue the command; the first write cycle sets up the block erase command, the second write cycle confirms the block erase command and latches the block address in the program/eras e controller and starts it. the sequence is aborted if the confirm command is not given and the device will output the status register data with bits 4 and 5 set to '1'. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operat ion the memory will only accept the read stat us register command and the program/erase suspend comm and. all other commands will be ignored. the command can be executed using either v dd (for a normal erase operation) or v pp (for a fast erase operation). if v pp is in the v pph range when the command is issued then a fast erase operation will be executed, otherwise the operation will use v dd . if v pp goes below the v pp lockout voltage, v pplk , during a fast erase the operation aborts, the status register v pp status bit is set to ?1? and the command must be re-issued. typical erase times are given in ta b l e 1 0 . see appendix b: flowcharts , figure 23: block erase flowchart and pseudocode , for a suggested flowchart on using the block erase command. 4.7 program command the program command is used to program the memory array. two bus write operations are required to issue the command; the first write cycle sets up the program command, the second write cycle latches the address and dat a to be programmed in the program/erase controller and starts it. a program operation can be aborted by writing ffffffffh to any address after the program set-up command has been given. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the program oper ation the memory will only accept the read status register command and the program/erase suspend comm and. all other commands will be ignored. if reset/power-down, rp , falls to v il during programming the op eration will be aborted. the command can be executed using either v dd (for a normal program operation) or v pp (for a fast program operation). if v pp is in the v pph range when the command is issued then a fast program operation will be exec uted, otherwise the operation will use v dd . if v pp goes below the v pp lockout voltage, v pplk , during a fast program the operation aborts and the status register v pp status bit is set to ?1?. as data integrity cannot be guaranteed when the program operation is aborted, the memory block must be erased and reprogrammed. see appendix b: flowcharts on page 58 , figure 21: program flowchart and pseudocode , for a suggested flowchart on using the program command.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb command interface 31/69 4.8 program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. the command will only be accepted du ring a program or erase operation. it can be issued at any time during a program or erase operation. the command is ignored if the device is already in suspend mode. one bus write cycle is required to issue th e program/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other comman ds will be accepted until the program/erase controller has paused. after the program/erase controller ha s paused, the memory will continue to output the status register until another command is issued. during the polling period between issuing the program/erase susp end command and the program/erase controller pausing it is possible for the operation to complete. once the program/erase controller status bit (bit 7) indicates that the program/erase controller is no longer active, the program suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to determine if the operation has completed or is suspended. for timing on the delay between issuing the program/erase suspend command and the program/erase controller pausing see ta b l e 1 0 . during program/erase suspend the read memory array, read status register, read electronic signature, read query and program/erase resume commands will be accepted by the command interface. additionally, if the suspended operation was erase then the program and the program su spend commands will also be accepted. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed correctly. see appendix b: flowcharts , figure 22: program suspend & resume flowchart and pseudocode , and figure 24: erase suspend & resume flowchart and pseudocode , for suggested flowcharts on using the program/erase suspend command. 4.9 program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the program/erase resume command. see appendix b: flowcharts , figure 22: program suspend & resume flowchart and pseudocode , and figure 24: erase suspend & resume flowchart and pseudocode , for suggested flowcharts on using the program/erase resume command.
command interface m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 32/69 4.10 set burst configurat ion register command the set burst configuration register command is used to write a new value to the burst configuration control register which defines the burst length, type, x and y latencies, synchronous/asynchronous r ead mode and the valid clock edge configuration. two bus write cycles are required to issue the set burst configuration register command. the first cycle writes the setup command and the address corresponding to the set burst configuration register content. the second cycle writes the burst configuration register data and the confirm command. once the command is issued the memory returns to read mode as if a read memory array command had been issued. the value for the burst configuration register is always presented on a0-a15. m0 is on a0, m1 on a1, etc.; the other address bits are ignored. table 9. commands (1) 1. x = don?t care; ra = read address, rd = read data, id = device code, srd = status register data, pa = program address; pd = program data, qa = query address, qd = query data, ba = any address in the block, bcr = burst configuration register value. command cycles bus operations 1st cycle 2nd cycle op. addr. data op. addr. data read memory array 2 write x ffh read ra rd read electronic signature (manufacturer code) 2 write x 90h read 00000h 20h read electronic signature (device code) 2 write x 90h read 00001h idh read electronic signature (burst configuration register) 2 write x 90h read 00005h bcrh read status register 2 write x 70h read x srdh read query 2 write x 98h read qah qdh clear status register 1 write x 50h block erase 2 write x 20h write bah d0h program 2 write x 40h 10h write pa pd program/erase suspend 1 write x b0h program/erase resume 1 write x d0h set burst configuration register 2 write x 60h write bcrh 03h
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb command interface 33/69 table 10. program, erase times and program, erase endurance cycles (1) 1. t a = ?40 to 125 c, v dd = 2.7 v to 3.6 v, v ddq = 2.4 v to v dd parameters m58bw016 unit min typ max v pp =v dd v pp =12v v pp =v dd v pp =12v parameter block (64 kb) program 0.030 0.016 0.060 0.032 s main block (512 kb) program 0.23 0.13 0.46 0.26 s parameter block erase 0.8 0.64 1.8 1.5 s main block erase 1.5 0.9 3 1.8 s program suspend latency time 310s erase suspend latency time 10 30 s program/erase cycles (per block) 100,000 cycles
status register m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 34/69 5 status register the status register provides information on the current or previous program or erase operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status register command can be issued. the status register is automatically read after program, erase or program/erase resume commands. the status register can be read from any address. the contents of the status register can be updated during an erase or program operation by toggling the output enable or output disable pins or by deactivating (chip enable, v ih ) and then reactivating (chip enable and output enable, v il , and output disable, v ih .) the device. the status register bits are summarized in table 11: status register bits . refer to ta b l e 1 1 in conjunction with the following text descriptions. 5.1 program/erase controller status (bit 7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is set to ?0?, the program/erase controller is active; when bit7 is set to ?1?, the program/erase controller is inactive. the program/erase controller status is set to ?0? immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is set to ?1?. during program and erase operations the program/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase controller completes the operation and the bit is set to ?1?. after the program/erase controller completes its operation the erase status (bit5), program status bits should be tested for errors. 5.2 erase suspend status (bit 6) the erase suspend status bit indicates that an erase operation has been suspended and is waiting to be resumed. the erase suspend status should only be considered valid when the program/erase controller status bit is set to ?1? (program/erase controller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is set to ?0?, the program/erase controller is active or has completed its operation; when the bit is set to ?1?, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the erase suspend status bit returns to ?0?.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb status register 35/69 5.3 erase status (bit 5) the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (p rogram/erase controller inactive). when the erase status bit is set to ?0?, the memory has successfully verified that the block has erased correctly. when the erase status bit is set to ?1?, the program/erase controller has applied the maximum number of pulses to the block an d still failed to verify that the block has erased correctly. once set to ?1?, the erase status bit can only be reset to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 5.4 program status (bit 4) the program status bit is used to identify a program failure. bit4 should be read once the program/erase controller status bit is high (program/erase controller inactive). when bit4 is set to ?0? the memory has successfully verified that the device has programmed correctly. when bit4 is set to ?1? the device has failed to verify that the data has been programmed correctly. once set to 1?, the program status bit can only be reset to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 5.5 v pp status (bit 3) the v pp status bit can be used to identify an invalid voltage on the v pp pin during fast program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. indeterminate results can occur if v pp becomes invalid during a fast program or erase operation. when the v pp status bit is set to ?0?, the voltage on the v pp pin was sampled at a valid voltage; when the v pp status bit is set to ?1?, the v pp pin has a voltage that is below the v pp lockout voltage, v pplk . once set to ?1?, the v pp status bit can only be reset to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail.
status register m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 36/69 5.6 program suspend status (bit 2) the program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bi t is set to ?1? (program/erase controller inactive); after a program/ erase suspend command is is sued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is set to ?0?, the program/erase controller is active or has completed its operation; when the bit is set to ?1?, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the program suspend status bit returns to ?0?. 5.7 block protection status (bit 1) the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is set to ?0?, no program or erase operations have been attempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is set to ?1?, a program or erase operation has been attempted on a protected block. once set to ?1?, the block protection status bit can only be reset low by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issu ed, otherwise the new co mmand will appear to fail. all others bits are reserved. table 11. status register bits bit name logic level definition 7 program/erase controller status ?1? ready ?0? busy 6 erase suspend status ?1? suspended ?0? in progress or completed 5erase status ?1? erase error ?0? erase success 4 program status, ?1? program error ?0? program success 3v pp status ?1? v pp invalid, abort ?0? v pp ok 2 program suspend status ?1? suspended ?0? in progress or completed 1 erase/program in a protected block ?1? program/erase on protected block, abort ?0? no operations to protected sectors other bits reserved
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb maximum ratings 37/69 6 maximum ratings stressing the device above the ratings listed in table 12: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 12. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ?40 125 c t stg storage temperature ?55 155 c v io input or output voltage ?0.6 v ddq +0.6 v ddqin +0.6 v v dd , v ddq, v ddqin supply voltage ?0.6 4.2 v v pp program voltage ?0.6 13.5 (1) 1. cumulative time at a high voltage level of 13.5 v should not exceed 80 hours on v pp pin. v
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 38/69 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 13: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. figure 6. ac measurement input/output waveform 1. v dd = v ddq . table 13. operating and ac measurement conditions parameter value units min max supply voltage (v dd )2.7 3.6v input/output supply voltage (v ddq )2.4 v dd v ambient temperature (t a ) grade 6 ?40 90 c grade 3 ?40 125 c load capacitance (c l )30pf clock rise and fall times 4 ns input rise and fall times 4 ns input pulses voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai04153 v ddq v ddqin 0 v v ddq /2 v ddqin /2
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 39/69 figure 7. ac measurement load circuit table 14. device capacitance (1)(2) 1. t a = 25 c, f = 1 mhz 2. sampled only, not 100% tested. symbol parameter test condition typ max unit c in input capacitance v in = 0 v 6 8 pf c out output capacitance v out = 0 v 8 12 pf ai04154 1.3 v out c l c l includes jig capacitance 3.3 k ? 1n914 device under test
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 40/69 table 15. dc characteristics symbol parameter test condition min max unit i li input leakage current 0 v v in v ddq 1 a i lo output leakage current 0 v v out v ddq 5 a i dd supply current (random read) e =v il , g =v ih , f add =6mhz m58bw016dt/b 20 ma m58bw016ft/b 25 i ddp-up (1) supply current (power-up) e =v ih applies only to m58bw016ft/b 20 ma i ddb supply current (burst read) e =v il , g =v ih , f clock =40mhz m58bw016dt/b 30 ma m58bw016ft/b e =v il , g =v ih , f clock =56mhz m58bw016dt/b 30 ma m58bw016ft/b 40 ma i dd1 supply current (standby) e =r p =v dd 0.2 v m58bw016dt/b 60 a m58bw016ft/b 150 a supply current (auto low-power) e =v ss 0.2v, rp =v dd 0.2v 60 a i dd2 supply current (reset/power-down) rp =v ss 0.2v 60 a i dd3 supply current (program or erase, set lock bit, erase lock bit) program, block erase in progress 30 ma i dd4 supply current (erase/program suspend) e =v ih m58bw016dt/b 40 a m58bw016ft/b 150 a i pp program current (read or standby) v pp v pp1 30 a i pp1 program current (read or standby) v pp v pp1 30 a i pp2 program current (power-down) rp =v il 5 a i pp3 program current (program) program in progress v pp =v pp1 200 a v pp =v pph 20 ma i pp4 program current (erase) erase in progress v pp =v pp1 200 a v pp =v pph 20 ma v il input low voltage ?0.5 0.2v ddqin v v ih input high voltage (for dq lines) 0.8v ddqin v ddq +0.3 v v ih input high voltage (for input only lines) 0.8v ddqin 3.6 v v ol output low voltage i ol = 100 a 0.1 v v oh output high voltage cmos i oh =?100a v ddq ?0.1 v v pp1 program voltage (program or erase operations) 2.7 3.6 v v pph program voltage (program or erase operations) 11.4 12.6 v v lko v dd supply voltage (erase and program lockout) 2.2 v v pplk v pp supply voltage (erase and program lockout) 11.4 v 1. i ddp-up is defined only during the power-up phase of the m58b w016ft/b, from the moment current is applied with rp low to the moment when the supply voltage has become stable and rp is brought to high.
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 41/69 figure 8. asynchronous bus read ac waveforms . table 16. asynchronous bus read ac characteristics symbol parameter test condition m58bw016 unit 70 80 t avav address valid to address valid e =v il , g =v il min 70 80 ns t avqv address valid to output valid e =v il , g =v il max 70 80 ns t axqx address transition to output transition e = v il , g = v il min 0 0 ns t ehlx chip enable high to latch enable transition min 0 0 ns t ehqx chip enable high to output transition g =v il min 0 0 ns t ehqz chip enable high to output hi-z g =v il max 20 20 ns t elqv (1) 1. output enable g may be delayed up to t elqv - t glqv after the falling edge of chip enable e without increasing t elqv . chip enable low to output valid g =v il max 70 80 ns t elqx chip enable low to output transition g =v il min 0 0 ns t ghqx output enable high to output transition e =v il min 0 0 ns t ghqz output enable high to output hi-z e =v il max 15 15 ns t glqv output enable low to output valid e =v il max 25 25 ns t glqx output enable to output transition e =v il min 0 0 ns t llel latch enable low to chip enable low min 0 0 ns ai04407c e g l a0-a18 dq0-dq31 valid tllel taxqx telqx telqv tavqv tglqx tglqv tehqx tehqz tghqx tghqz see also page read output tehlx tavav gd
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 42/69 figure 9. asynchronous latch controlled bus read ac waveforms table 17. asynchronous latch controlled bus read ac characteristics symbol parameter test condition m58bw016 unit 70 80 t avll address valid to latch enable low e =v il min 0 0 ns t ehlx chip enable high to latch enable transition min 0 0 ns t ehqx chip enable high to output transition g =v il min 0 0 ns t ehqz chip enable high to output hi-z g =v il max 20 20 ns t elll chip enable low to latch enable low min 0 0 ns t ghqx output enable high to output transition e =v il min 0 0 ns t ghqz output enable high to output hi-z e =v il max 15 15 ns t glqv output enable low to output valid e =v il max 25 25 ns t glqx output enable low to output transition e =v il min 0 0 ns t lhax latch enable high to address transition e =v il min 5 5 ns t lhll latch enable high to latch enable low min 10 10 ns t lllh latch enable low to latch enable high e =v il min 10 10 ns t llqv latch enable low to output valid e =v il , g =v il max 70 80 ns t llqx latch enable low to output transition e =v il , g =v il min 0 0 ns ai03645 l e g a0-a18 dq0-dq31 valid tehlx tlhll tlhax tavll telll tlllh tehqx tehqz tghqx ghqz tllqx tllqv tglqx tglqv see also page read output
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 43/69 figure 10. asynchronous page read ac waveforms table 18. asynchronous page read ac characteristics (1) 1. for other timings see table 16: asynchronous bus read ac characteristics . symbol parameter test condition m58bw016 unit 70 80 t avqv1 address valid to output valid e =v il , g =v il max 25 25 ns t axqx address transition to output transition e =v il , g =v il min 6 6 ns ai03646 a0-a1 dq0-dq31 a0 and/or a1 tavqv1 output taxqx output + 1
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 44/69 figure 11. asynchronous write ac waveforms ai03651 dq0-dq31 w rp a0-a18 e = l g input valid valid twheh valid tavwh twlwh telwl input valid sr v pp twhax twhwl twhdx tdvwh twhgl twhqv tvphwh tqvvpl tqvpl tphwh rp = v dd rp = v hh read status register write cycle write cycle tavll
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 45/69 figure 12. asynchronous latch controlled write ac waveforms ai03652 dq0-dq31 w rp a0-a18 l g input valid valid valid tavlh input valid sr v pp tlhax read status register write cycle write cycle e tlllh tllwh twhax telwl twlwh twheh twhwl twhgl twhqv tdvwh twhdx tvphwh tqvvpl tqvpl rp = v hh rp = v dd tavwh telll tavll
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 46/69 table 19. asynchronous write and latch controlled write ac characteristics symbol parameter test condition m58bw016 unit 70 80 t avll address valid to latch enable low min 0 0 ns t avwh address valid to write enable high e =v il min 50 50 ns t dvwh data input valid to write enable high e =v il min 50 50 ns t elll chip enable low to latch enable low min 0 0 ns t elwl chip enable low to write enable low min 0 0 ns t lhax latch enable high to address transition min 5 5 ns t lllh latch enable low to latch enable high min 10 10 ns t llwh latch enable low to write enable high e =v il min 50 50 ns t qvvpl output valid to v pp low min 0 0 ns t vphwh v pp high to write enable high min 0 0 ns t whax write enable high to address transition e =v il min 0 0 ns t whdx write enable high to input transition e =v il min 0 0 ns t wheh write enable high to chip enable high min 0 0 ns t whgl write enable high to output enable low min 150 150 ns t whqv write enable high to output valid min 175 175 ns t whwl write enable high to write enable low min 20 20 ns t wlwh write enable low to write enable high e =v il min 60 60 ns t qvpl output valid to reset/power-down low min 0 0 ns
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 47/69 figure 13. synchronous burst read (data valid from ?n? clock rising edge) ai04409 dq0-dq31 a0-a18 l e g k valid tkhax n+2 n+1 n 1 0 tkhll tllkh telll tavll tkhlx tehqx tehqz tghqx tghqz tglqv setup output tkhqv tqvkh tavqv note : n depends on burst x-latency.
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 48/69 figure 14. synchronous burst read (data valid from ?n? clock rising edge) 1. for set up signals and timing s see synchronous burst read. table 20. synchronous burst read ac characteristics (1) 1. for other timings see table 16: asynchronous bus read ac characteristics . symbol parameter test condition m58bw016 unit 70 80 t avll address valid to latch enable low e =v il min 0 0 ns t bhkh burst address advance high to valid clock edge e =v il , g =v il , l =v ih min 8 8 ns t blkh burst address advance low to valid clock edge e =v il , g =v il , l =v ih min 8 8 ns t elll chip enable low to latch enable low min 0 0 ns t glqv output enable low to output valid e =v il , l =v ih min 25 25 ns t khax valid clock edge to address transition e =v il min 5 5 ns t khll valid clock edge to latch enable low e =v il min 0 0 ns t khlx valid clock edge to latch enable transition e =v il min 0 0 ns t khqx valid clock edge to output transition e =v il , g =v il , l =v ih m58bw016dt/b min 3 3 ns m58bw016ft/b min 2 2 ns t llkh latch enable low to valid clock edge e =v il m58bw016dt/b min 6 6 ns m58bw016ft/b min 5 5 ns t qvkh (2) 2. data output should be read on the valid clock edge. output valid to valid clock edge e =v il , g =v il , l =v ih min 6 6 ns t rlkh valid data ready low to valid clock edge e =v il , g =v il , l =v ih min 6 6 ns t khqv valid clock edge to output valid e =v il , g =v il , l =v ih max 11 11 ns ai04408b k n+5 n+4 n+3 n+2 n+1 n dq0-dq31 tqvkh tkhqx q0 q1 q2 q3 q4 q5 setup burst read q0 to q3 tkhqv note: n depends on burst x-latency
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 49/69 figure 15. synchronous burst read - continuous - valid data ready output 1. valid data ready = vali d low during valid clock edge 2. v= valid output. 3. r is an open drain output with an internal pull up resistor of 1 m ?. the internal timing of r follows dq. an external resistor, typically 300 k ?. for a single memory on the r bus, should be used to gi ve the data valid set up time required to recognize that valid data is availabl e on the next valid clock edge. figure 16. synchronous burst read - burst address advance ai03649 k output (1) vvvv trlkh r v (2) ai03650 k add q0 q1 l q2 add valid g tglqv tblkh tbhkh b
dc and ac parameters m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 50/69 figure 17. reset, power-down and power-up ac waveforms - control pins low figure 18. reset, power-down and power-up ac waveforms - control pins toggling ai14240 w, rp tphwl tphel tphgl g, e vdd, vddq tvdhph tphwl tphel tphgl tplph tplrz power-up reset r l tphll hi-z hi-z tphrh ai14241 w, rp tphwl tphel tphgl g, e vdd, vddq tvdhph tplph tplrz power-up reset r l tphll hi-z hi-z tphrh tphrh tglrh telrh tllrh twlrh
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb dc and ac parameters 51/69 table 21. reset, power-down and power-up ac characteristics symbol parameter min max unit t phel reset/power-down high to chip enable low 50 ns t phll reset/power-down high to latch enable low 50 ns t phqv (1) 1. this time is t phel + t avqv or t phel + t elqv . reset/power-down high to output valid 95 ns t phwl reset/power-down high to write enable low 50 ns t phgl reset/power-down high to output enable low 50 ns t plph reset/power-down low to re set/power-down high 100 ns t phrh (1) reset/power-down high to valid data ready high 95 t vdhph supply voltages high to reset/power-down high m58bw016dt/b 10 s m58bw016ft/b 50 s t plrz reset/power-down low to data ready high impedance 80 ns t wlrh write enable low to data ready high impedance 80 ns t glrh output enable low to data ready high impedance 80 ns t elrh chip enable low to data ready high impedance 80 ns t llrh latch enable low to data ready high impedance 80 ns
package mechanical m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 52/69 8 package mechanical figure 19. pqfp80 - 80 lead plastic quad flat pack, package outline 1. drawing is not to scale. table 22. pqfp80 - 80 lead plastic quad flat pack, package mechanical data symbol millimeters inches typ min max typ min max a 3.400 0.1339 a1 0.250 0.0098 a2 2.800 2.550 3.050 0.1102 0.1004 0.1201 b 0.300 0.450 0.0118 0.0177 c 0.130 0.230 0.0051 0.0091 d 23.200 22.950 23.450 0.9134 0.9035 0.9232 d1 20.000 19.900 20.100 0.7874 0.7835 0.7913 d2 18.400 ? ? 0.7244 ? ? e 0.800 ? ? 0.0315 ? ? e 17.200 16.950 17.450 0.6772 0.6673 0.6870 e1 14.000 13.900 14.100 0.5512 0.5472 0.5551 e2 12.000 ? ? 0.4724 ? ? l 0.800 0.650 0.950 0.0315 0.0256 0.0374 l1 1.600 ? ? 0.0630 ? ? a0707 n80 80 nd 24 24 ne 16 16 qfp-b d1 cp b e a2 a n l a1 e1 e2 1 d c e d2 l1 nd ne
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb package mechanical 53/69 figure 20. lbga80 10 12 mm - 8 10 active ball array, 1 mm pitch, package outline 1. drawing is not to scale. table 23. lbga80 10 12 mm - 8 10 active ball array, 1 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.700 0.0669 a1 0.350 0.0138 a2 1.100 0.0433 b 0.500 0.0197 d 10.000 ? ? 0.3937 ? ? d1 7.000 ? ? 0.2756 ? ? ddd 0.120 0.0047 e 12.000 ? ? 0.4724 ? ? e1 9.000 ? ? 0.3543 ? ? e 1.000 ? ? 0.0394 ? ? fd 1.500 ? ? 0.0591 ? ? fe 1.500 ? ? 0.0591 ? ? sd 0.500 ? ? 0.0197 ? ? se 0.500 ? ? 0.0197 ? ? e1 e d1 d eb a2 a1 a bga-z05 ddd fd fe sd se e ball "a1"
part numbering m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 54/69 9 part numbering note: devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 24. ordering information scheme example: m58 bw016d t 80 t 3 f t device type m58 architecture b = burst mode operating voltage w = v dd = 2.7 v to 3.6 v; v ddq = v ddqin = 2.4 to v dd device function 016d = 16 mbit (x 32), boot block, burst, 0.15 m 016f = 16 mbit (x 32), boot block, burst, 0.11 m array matrix t = top boot b = bottom boot speed 70 = 70 ns 80 = 80 ns package t = pqfp80 za = lbga 10 12 mm temperature range 3 = automotive grade certified (1) , ?40 to 125 c 1. qualified & characteriz ed according to aec q100 & q003 or equiva lent, advanced screening according to aec q001 & q002 or equivalent. version f = silicon version f option t = tape and reel packing f = ecopack package, tape and reel packing
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb common flash interface (cfi) 55/69 appendix a common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. ta bl e 2 5 , ta bl e 2 6 , ta b l e 2 7 , ta b l e 2 8 and ta bl e 2 9 show the addresses used to retrieve the data. table 25. query structure overview offset sub-section name description 00h manufacturer code 01h device code 10h cfi query identification string comm and set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash memory layout p(h) (1) 1. offset 15h defines p which points to the pr imary algorithm exten ded query address table. primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) 2. offset 19h defines a which points to the al ternate algorithm extended query address table. alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) table 26. cfi - query address and data output (1)(2) 1. the x 8 or byte address and the x 16 or word address mode are not available. 2. query data are always presented on dq7-dq0. dq31-dq8 are set to '0'. address a0-a18 data instruction 10h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 11h 52h "r" 12h 59h "y" 13h 03h primary vendor: command set and control interface id code 14h 00h 15h 35h primary algorithm extended query address table: p(h) 16h 00h 17h 00h alternate vendor: command set and control interface id code 18h 00h 19h 00h alternate algorithm extended query address table 1ah 00h
common flash interface (cfi) m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 56/69 table 27. cfi - device voltage and timing specification address a0-a18 data description 1bh 27h (1) 1. bits are coded in binary code decimal, bit7 to bi t4 are scaled in volts and bit3 to bit0 in mv. v dd min, 2.7 v 1ch 36h (1) v dd max, 3.6 v 1dh b4h (2) 2. bit7 to bit4 are coded in hexadecimal and scaled in vo lts while bit3 to bit0 ar e in binary code decimal and scaled in 100 mv. v pp min 1eh c6h (2) v pp max 1fh 04h 2 n ms typical time-out for word, dword prog ? not available 20h 00h 2 n ms, typical time-out for max buffer write ? not available 21h 0ah 2 n ms, typical time-out for erase block 22h 00h 2 n ms, typical time-out for chip erase ? not available 23h-24h reserved 25h 04h 2 n x typical for individual block erase time-out maximum 26h 00h 2 n x typical for chip erase max time-out ? not available table 28. device geometry definition address a0-a18 data description 27h 15h 2 n number of bytes memory size 28h 03h device interface sync./async. 29h 00h organization sync./async. 2ah 00h page size in bytes, 2 n 2bh 00h 2ch 02h bit7-0 = number of erase block regions in device 2dh 1eh number (n-1) of blocks of identical size; n=31 2eh 00h 2fh 00h erase block region information x 256 bytes per erase block (64 kbytes) 30h 01h 31h 07h number (n-1) of blocks of identical size; n=8 32h 00h 33h 20h erase block region information x 256 bytes per erase block (8 kbytes) 34h 00h
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb common flash interface (cfi) 57/69 table 29. extended query information address offset address a18-a0 data (hex) description (p)h 35h 50h "p" query ascii string - extended table (p+1)h 36h 52h "r" (p+2)h 37h 49h "y" (p+3)h 38h 31h major version number (p+4)h 39h 31h minor version number (p+5)h 3ah 86h optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, lock/unlock supported (1=yes) bit4, queue erase supported (0=no) bit 31-5 reserved for future use (p+6)h 3bh 01h optional features: synchronous read supported (p+7)h 3ch 00h (p+8)h 3dh 00h (p+9)h 3eh 01h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h 3fh reserved
flowcharts m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 58/69 appendix b flowcharts figure 21. program flowchart and pseudocode 1. if an error is found, the status register must be cleared before further p/e operations. write 40h ai03850b start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 v pp invalid error (1) program error (1) program command: ? write 40h ? write address & data (memory enters read status state after the program command) do: ? read status register (e or g must be toggled) while b7 = 0 if b3 = 1, v pp invalid error: ? error handler if b4 = 1, program error: ? error handler yes end no b1 = 0 program to protect block error if b1 = 1, program to protected block error: ? error handler yes
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb flowcharts 59/69 figure 22. program suspend & resume flowchart and pseudocode write 70h ai00612b read status register yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 0 if b2 = 0, program completed read memory array command: ? write ffh ? one or more data reads from other blocks write d0h program erase resume command: ? write d0h to resume erasure ? if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
flowcharts m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 60/69 figure 23. block erase flowchart and pseudocode 1. if an error is found, the status register must be cleared before further p/e operations. write 20h ai03851b start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4 and b5 = 1 v pp invalid error (1) command sequence error erase command: ? write 20h ? write block address (a11-a18) & d0h (memory enters read status state after the erase command) do: ? read status register (e or g must be toggled) if erase command given execute suspend erase loop while b7 = 0 if b3 = 1, v pp invalid error: ? error handler if b4, b5 = 1, command sequence error: ? error handler no no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: ? error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: ? error handler
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb flowcharts 61/69 figure 24. erase suspend & resume flowchart and pseudocode write 70h ai00615b read status register yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 0 if b6 = 0, erase completed read memory array command: ? write ffh ? one or more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: ? write d0h to resume the erase operation ? if the erase operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
flowcharts m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 62/69 figure 25. power-up sequence followed by synchronous burst read ai03834b power-up or reset asynchronous read write 60h command write 03h with a15-a0 bcr inputs synchronous read bcr bit 15 = '1' set burst configuration register command: ? write 60h ? write 03h and bcr on a15-a0 bcr bit 15 = '0'
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb flowcharts 63/69 figure 26. command interface and program/erase controller flowchart (a) ai03835 read elec. signature yes no 90h read status yes 70h no erase set-up yes 20h no program set-up yes 40h no clear status yes 50h no wait for command write read status read array yes d b c read cfi yes 98h no no d0h a erase command error e d
flowcharts m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 64/69 figure 27. command interface and program/erase controller flowchart (b) ai03836b set bcr set_up yes 60h no d ffh 03h no yes no e yes
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb flowcharts 65/69 figure 28. command interface and program/erase controller flowchart (c) read status 70h b erase ready no a b0h no read status yes ready no erase suspend yes read array yes erase suspended read status yes no 40h no d0h no program set_up ai03837 yes yes no yes read status c
flowcharts m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 66/69 figure 29. command interface and program/erase controller flowchart (d) read status 70h b program ready no c b0h no read status yes ready no program suspend read array yes program suspended read status yes no no d0h ai03838 yes no yes read status yes
m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb revision history 67/69 revision history table 30. document revision history date version changes january-2001 01 first issue. 05-jun-2001 02 major rewrite and restructure. 15-jun-2001 03 nd and ne values changed in pqfp80 package mechanical table. 17-jul-2001 04 pqfp80 package outline drawing and mechanical data table updated. 17-dec-2001 05 t lead removed from absolute maximum ratings ( ta b l e 1 2 ). 80, 90 and 100 ns speed classes defined ( ta bl e 1 6 , ta bl e 1 7 , ta bl e 1 8 , ta b l e 1 9 and ta b l e 2 0 clarified accordingly). figure 13 , figure 14 , figure 15 and figure 16 clarified. temperature range 3 and 6 added. ta b l e 1 3 , ta b l e 1 4 , ta b l e 1 5 , ta bl e 2 1 and cfi ta bl e 2 6 , ta bl e 2 7 , ta b l e 2 8 , ta b l e 2 9 clarified. document status changed from product preview to preliminary data. 17-jan-2002 06 dc characteristics i pp , i pp1 and i dd1 clarified. ac bus read characteristics timing t ghqz clarified. 30-aug-2002 6.1 revision numbering modified: a minor revision will be indicated by incrementing the tenths digit, and a major revision, by incrementing the units digit of the previous version (e.g. revision version 06 becomes 6.0). references of v pp pin used for block protection purposes removed. figure 8 modified. 4-sep-2002 7.0 datasheet status changed from preliminary data to full datasheet. t wlwh parameter modified in table 19: asynchronous write and latch controlled write ac characteristics . 13-may-2003 7.1 revision history moved to end of document. v pp clarified in program and block erase commands and status register, v pp status bit. v pplk added to dc characteristics table. timing t khqv modified. 16-oct-2003 7.2 silicon version added to ordering information scheme. 03-mar-2005 8.0 tuning block protection feature removed from the whole document and root part numbers m58bw016bt/b have been removed. figure 21 , figure 22 , figure 23 , figure 24 , figure 25 and figure 27 updated. lbga80 package (za) removed. lead-free option added. 90 and 100 ns access times removed and 70 ns added. temperature rage 6 removed from table 24: ordering information scheme . 06-sep-2005 9.0 load capacitance updated in table 13: operating and ac measurement conditions . 3-mar-2006 10.0 updated table 24: ordering information scheme on page 54 and disclaimer information. converted document to new template. 16-jun-2006 11 m58bw016ft and m58bw016fb part numbers added. small text changes.
revision history m58bw016dt, M58BW016DB, m58bw016ft, m58bw016fb 68/69 09-nov-2006 12 lbga80 package added (see figure 20 and ta bl e 2 3 ). m58bw016ft and m58bw016fb behavior in burst mode specified under section 3.2.1: synchronous burst read . i ddb , i dd1 and i dd4 current values specified for m58bw016ft and m58bw016fb in table 15: dc characteristics , i dd5 added. t vdhph specified for m58bw016ft and m58bw016fb in table 21: reset, power-down and power-up ac characteristics . t khqx specified for m58bw016ft and m58bw016fb in table 20: synchronous burst read ac characteristics . 23h-24h reserved in table 27: cfi - device voltage and timing specification . 3fh reserved in table 29: extended query information . 24-nov-2006 13 i dd current specified for m58bw016dt/b and m58bw016ft/b in table 15: dc characteristics . 05-oct-2007 14 table 7: burst configuration register and table 21: reset, power-down and power-up ac characteristics updated. modified values for t llkh in table 20: synchronous burst read ac characteristics . figure 17: reset, power-down and power-up ac waveforms - control pins low updated and figure 18: reset, power-down and power-up ac waveforms - control pins toggling added. small text changes. table 30. document revision history (continued) date version changes
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